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LOKESH.

@avnlk — github · codeforces · linkedin · atcoder · leetcode

Integrated M.Tech, IIIT Bangalore (2027) | Systems Performance | FPGA & HLS | Algorithmic Engineering

I design hardware and software that doesn't wait around, from 5G-NR physical layer IP cores to kernel-level protocol tracing and high-performance algorithms. Currently chasing nanoseconds across the stack, building low-latency systems where every clock cycle is measured.

clk · rising edge triggered · targeting sub-µs latency

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about

Started in FPGA implementation of 5G-NR physical layer — interleavers, deinterleavers, the unglamorous plumbing that makes wireless work; and realized the thing I actually love is the constraint itself: how fast can this go before it breaks.

That question has taken me through Vivado HLS pipelines, kernel-level protocol benchmarking across 9.9M measurements, and algorithmic problem solving;The same obsession with efficiency applies whether you are routing logic on an FPGA or managing syscalls in an operating system.

1731

Codeforces Peak Rating · Expert

5G-NR FPGA IP cores built · Paper draft in progress

9.9M

latency measurements · TCP/REST/gRPC teardown

long-term goal: latency, not features

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work

Competitive Programming & Algorithmic Engineering

ACTIVE

Learning C++ data structures, and low-latency algorithmic problem solving. Achieved an Expert rating (peak 1731) on Codeforces and represented IIIT-B at the ICPC preliminary rounds (Team SSL). Graphs is my favourite topic.

Codeforces rating · 44 contests

C++ Algorithms Codeforces Expert ICPC

Protocol Performance Analysis

SHIPPED

Kernel-level teardown of TCP, REST, and gRPC on Ubuntu 24.04 with uniform protobuf serialization. 9.9M latency measurements across 75 experiments (5 message sizes × 5 concurrency levels × 3 protocols). Exposed 121× tail amplification and traced page fault step function at 32KB to Go's _MaxSmallSize = 32768 allocator constant.

P99/P50 tail ratio · log scale

Go Protobuf gRPC Linux kernel profiling

read writeup

5G-NR Physical Layer Interleavers & Deinterleavers

IN PROGRESS

Six Vivado HLS IP cores so far; channel, bit, and sub-block interleavers and de-interleavers, across PDCCH/PUCCH/PDSCH. Started as three separate course assignments; ended up beating the course instructor's own published results by 18–19× on a device with far fewer resources. Zero runtime division across every datapath built so far, proven exact via seven formal theorems. Drafting for IEEE TCAS-I.

Latency vs. published baseline

Vivado HLS AXI-Stream Spartan-7 5G-NR 3GPP TS 38.212

read summary

Systolic Digital Compute-in-Memory (DCIM)

UNDER REVIEW

9×4 SRAM array for CNN inference via systolic array topology. Novel in-memory compute architecture with tiling-based scalability. Submitted to conference; currently under review.

SRAM systolic array CNN inference in-memory compute

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publications

Energy-Efficient IoT-Based Waterproof Irrigation Node Using Wireless Tree-Topology

PUBLISHED

Solar-powered waterproof sensor node for smart irrigation using nRF24L01 transceiver in a hierarchical tree-topology WSN. 3D-printed PLA casing with silica gel + epoxy seal. 7+ days operation without sunlight via sleep/wake cycles. 120m reliable range, $15 USD per node.

IEEE 2026 IoT WSN nRF24L01 Arduino

view on IEEE Xplore

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log

Summer 2026

Samsung R&D Institute Bangalore (SRIB)

Beyond 5G team, Advanced Protocols sub-group. Built a LSTM burst-prediction model. Built a pipeline tool: a drag-and-drop ML platform.

2026

APSCON 2026 Conference Acceptance

Research accepted on an energy-efficient IoT-based waterproof irrigation node utilizing wireless tree topology.

2025 – 2026

5G-NR FPGA IP Cores

6 interleaver/deinterleaver cores for PDCCH/PUCCH/PDSCH channels, now a journal draft. Vivado HLS, Spartan-7.

2025

Protocol Performance Benchmarking

9.9M latency measurements. TCP vs REST vs gRPC. Root-caused page fault step function to Go allocator.

ongoing

Competitive Programming

C++ and; Active on Codeforces, AtCoder, LeetCode — all @avnlk.

2027

Integrated M.Tech — IIIT Bangalore

ECE. Graduating 2027. Hardware-software co-design, low-latency systems, algorithmic engineering.

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contact

Open to conversations about FPGA design, low-latency systems, systems performance, or competitive programming. I'm @avnlk everywhere.

email github linkedin codeforces resume