Low-Latency Systems • FPGA • C++
[projects]
protocol_performance_analysis →
Kernel-level teardown of TCP, REST, and gRPC. Exposing the hidden syscall costs and 121× tail amplification behind protocol abstractions.
triangular_interleaver →
0.41µs end to end latency (~13.6× speedup) achieved by bypassing 3GPP algorithmic bottlenecks with BRAM-based O(1) memory lookups.
128pt_fft_dsp48_opt →
Radix-2 DIT FFT using DSP48 IP blocks. Optimized via sequential resource sharing to fit a 128-pt transform on 71% of Basys3 DSP capacity.